#4 WHAT’S THE NEWS? – KEEP UP TO DATE!
IMPROVING HLS FLOWS WITH A SMART HARDWARE GENERATION
August 29, 2022
HOW TO AVOID RE-SPINS IN DIGITAL ASIC/IC PROJECTS – CORRECT-BY-CONSTRUCTION WITH FORMAL
August 29, 2022
For us it’s time to spice up our secret sauce!
Improved Verification IP generation: We aim to reduce the properties to a bare minimum by removing any redundancies. On top of that we are improving the readability of our properties.
New type of Verification IP: We use our new type to find multi instruction bugs in your pipelined designs.
GUI update: The interface shows information extracted from our engine: e.g. the FSM of the model.
We are about to start our first alpha test, feel free to ask for a demo.
