The recent Wilson Research Group Functional Verification Study analyzed how verification nowadays influences the way ASIC/IC projects are managed. The numbers indicate that companies spent a majority of time and resources on IC verification. Verification Engineers spend 41% of their time debugging bugs. Half of those bugs can be classified as functional or logic flaws. 68% of the project require at …
For us it’s time to spice up our secret sauce! Improved Verification IP generation: We aim to reduce the properties to a bare minimum by removing any redundancies. On top of that we are improving the readability of our properties. New type of Verification IP: We use our new type to find multi instruction bugs in your pipelined designs. …
LUBIS EDA works on a novel solution to generate a synthesizable hardware design from an abstract software model. Our goal is to enhance conventional High-Level Synthesis (HLS) flows by making it suitable for control-oriented designs (e.g., controllers or a bus). As shown in in the figure above, our flow starts with a SystemC model that is analyzed and …