Blogs

Assertion-first hardware design: where properties and intent come first

Pitfalls in FPV

Verification
A RECORD OF LUBIS EDA
#1 WHAT’S THE NEWS? – KEEP UP TO DATE!
AGILE HARDWARE DEVELOPMENT IS NOT A THING! IS IT?
#2 WHAT’S THE NEWS? – KEEP UP TO DATE!
WRITING FORMAL PROPERTIES IS COMPLICATED? LET US DEMOCRATISE PROPERTY CREATION!
#3 WHAT’S THE NEWS? – KEEP UP TO DATE!
HOW TO AVOID RE-SPINS IN DIGITAL ASIC/IC PROJECTS – CORRECT-BY-CONSTRUCTION WITH FORMAL
#4 WHAT’S THE NEWS? – KEEP UP TO DATE!
IMPROVING HLS FLOWS WITH A SMART HARDWARE GENERATION

Training Topics

  1. Abstraction vectors (time, functionality)
  2. AIP for protocols
  3. AIP orchestration
  4. BMC & IPG, invariants
  5. Codestyle
  6. Completeness
  7. Liveness property, safety property
  8. Non-determinism (abstraction technique)
  9. Response generation (abstraction technique)
  10. Scoreboard (abstraction technique)
  11. Signal cutting, blackboxing
  12. State space explosion and mitigation techniques
  13. SVA fundamentals
  14. Whitebox checking, blackbox checking, greybox checking
  15. Witness, vacuity, reachability

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