Blogs

If you can’t reproduce it next week, it isn’t sign-off evidence: reproducible formal verification results and why formal needs history
Why jagged AI makes formal verification more important
Proof complexity in formal verification
Top 5 mistakes in formal verification adoption – how to build a system that sticks
LUBIS EDA 2025 review: scaling formal verification and preparing for 2026
Why Determinism still matters in the age of AI Verification
Assertion-first hardware design: where properties and intent come first
What makes a verification environment ‘Formal-Ready’?

Pitfalls in FPV

Verification
Why formal verification is important for semiconductor development
A RECORD OF LUBIS EDA

A RECORD OF LUBIS EDA

Company
#1 WHAT’S THE NEWS? – KEEP UP TO DATE!
AGILE HARDWARE DEVELOPMENT IS NOT A THING! IS IT?
#2 WHAT’S THE NEWS? – KEEP UP TO DATE!
WRITING FORMAL PROPERTIES IS COMPLICATED? LET US DEMOCRATISE PROPERTY CREATION!
#3 WHAT’S THE NEWS? – KEEP UP TO DATE!
How to avoid ASIC & IC re-spins with formal verification
#4 WHAT’S THE NEWS? – KEEP UP TO DATE!
IMPROVING HLS FLOWS WITH A SMART HARDWARE GENERATION

Training Topics

  1. Abstraction vectors (time, functionality)
  2. AIP for protocols
  3. AIP orchestration
  4. BMC & IPG, invariants
  5. Codestyle
  6. Completeness
  7. Liveness property, safety property
  8. Non-determinism (abstraction technique)
  9. Response generation (abstraction technique)
  10. Scoreboard (abstraction technique)
  11. Signal cutting, blackboxing
  12. State space explosion and mitigation techniques
  13. SVA fundamentals
  14. Whitebox checking, blackbox checking, greybox checking
  15. Witness, vacuity, reachability

Become a leader in formal verification