Assertion-first hardware design: where properties and intent come first

Assertion-first hardware design: where properties and intent come first Compute is the bottleneck. Not ideas. Not talent. Compute. Every major leap we care about over the next decade, from AI to medicine to energy and mobility, depends on chips that deliver more performance with less power, on tighter schedules than ever. RTL can be produced …

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Debugging for faster time to market: Insights into LUBIS EDA from an independent European case study

Formal verification startup LUBIS EDA: European IP case study A formal verification startup, LUBIS EDA, is at the center of this independent case study published by the European IP Helpdesk, highlighting how deep-tech innovation, formal verification, and intellectual property intersect in practice. Some bugs are loud. Most are quiet. In modern microchips, many design errors …

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Training Topics

  1. Abstraction vectors (time, functionality)
  2. AIP for protocols
  3. AIP orchestration
  4. BMC & IPG, invariants
  5. Codestyle
  6. Completeness
  7. Liveness property, safety property
  8. Non-determinism (abstraction technique)
  9. Response generation (abstraction technique)
  10. Scoreboard (abstraction technique)
  11. Signal cutting, blackboxing
  12. State space explosion and mitigation techniques
  13. SVA fundamentals
  14. Whitebox checking, blackbox checking, greybox checking
  15. Witness, vacuity, reachability

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