What’s the news? Within this series we keep you updated on our mission to provide you tools for your Agile Hardware Development! Follow us to stay informed on our correct-by-construction hardware generation. #correct-by-construction
Agile hardware development is not a thing! is it? In the world of software development many companies have switched to agile design methods.As a result, they achieve a faster time to market, fewer bugs, and a higher return on investment compared to traditional approaches. The Challenges of Applying Agile Methods to Hardware Design There is …
WHAT’S THE NEWS? Within this series we at LUBIS EDA keep you updated on our mission to provide you tools for your Agile Hardware Development! LUBIS IDE is here: We are happy to present our first version of our new IDE. The time of error prone fiddling within the terminal is over.Parsing, debugging and generating all …
Writing formal properties is completed? Let us democratize property creation! Today, formal verification is mostly used for bug hunting. Writing formal properties is time consuming and requires a certain level of expertise. The performance of formal tools increased drastically within the last decade. Trends like increasing design complexity, safety and security requirements (e.g. ISO 26262) …
At LUBIS EDA, Summer is coming! We used the time before the easter break for a spring-clean.We worked on our code base to set our selfs up to ship new features within the next months. I guess you’re here for the new features. Let’s take a look: Full support of arrays:We extended our subset to …
Avoid digital ASIC/IC re-spins using correct by construction formal verification The recent Wilson Research Group Functional Verification Study analyzed how verification nowadays influences the way ASIC/IC projects are managed. The numbers indicate that companies spent a majority of time and resources on IC verification. Verification Engineers spend 41% of their time debugging bugs. Half of those …
For us it’s time to spice up our secret sauce! Improved Verification IP generation: We aim to reduce the properties to a bare minimum by removing any redundancies. On top of that we are improving the readability of our properties. New type of Verification IP: We use our new type to find multi instruction bugs in your pipelined designs. …
IMPROVING HLS FLOWS WITH A SMART HARDWARE GENERATION LUBIS EDA works on a novel solution to generate a synthesizable hardware design from an abstract software model. Our goal is to enhance conventional High-Level Synthesis (HLS) flows by making it suitable for control-oriented designs (e.g., controllers or a bus). As shown in in the figure above, our flow starts …
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