Thank you very much for tuning into our first blogpost! To explain the origin story of LUBIS EDA`s, we need to take a small trip back to 2015. It all started, when I was reading a fellow PhD’s work on Path-Predicate Abstractions (PPA), looking for inspiration for my own research. The work of my college was focusing on …
Within this series we keep you updated on our mission to provide you tools for your Agile Hardware Development! LUBIS IDE is coming:The time of error prone fiddling with the terminal is (almost) over. We started implementing a first MVP for our GUI. Keep tuned for updates on the matter in the future. Plug & Play …
In the world of software development many companies have switched to agile design methods, achieving a faster time to market, fewer bugs and an increased ROI compared to traditional approaches. This sounds great, so why isn’t Agile Hardware Development a thing, yet? There is a great variety of agile methods for software, e.g., Test-Driven Development (TDD), Extreme Program-ming (XP) or Continuous Integration (CI). What all these …
Within this series we at LUBIS EDA keep you updated on our mission to provide you tools for your Agile Hardware Development! LUBIS IDE is here: We are happy to present our first version of our new IDE. The time of error prone fiddling within the terminal is over.Parsing, debugging and generating all in one place. …
Today, formal verification is mostly used for bug hunting. Writing formal properties is time consuming and requires a certain level of expertise. The performance of formal tools increased drastically within the last decade. Trends like increasing design complexity, safety and security requirements (e.g. ISO 26262) lead to an increasing usage of formal to verify the …
At LUBIS EDA, Summer is coming! We used the time before the easter break for a spring-clean.We worked on our code base to set our selfs up to ship new features within the next months. I guess you’re here for the new features. Let’s take a look: Full support of arrays:We extended our subset to …
The recent Wilson Research Group Functional Verification Study analyzed how verification nowadays influences the way ASIC/IC projects are managed. The numbers indicate that companies spent a majority of time and resources on IC verification. Verification Engineers spend 41% of their time debugging bugs. Half of those bugs can be classified as functional or logic flaws. 68% of the project require at …
For us it’s time to spice up our secret sauce! Improved Verification IP generation: We aim to reduce the properties to a bare minimum by removing any redundancies. On top of that we are improving the readability of our properties. New type of Verification IP: We use our new type to find multi instruction bugs in your pipelined designs. …
LUBIS EDA works on a novel solution to generate a synthesizable hardware design from an abstract software model. Our goal is to enhance conventional High-Level Synthesis (HLS) flows by making it suitable for control-oriented designs (e.g., controllers or a bus). As shown in in the figure above, our flow starts with a SystemC model that is analyzed and …