Leveraging formal verification to find critical RTL bugs in a RISC-V core – a LUBIS EDA best practice
RISC-V Formal Verification : Finding Critical RTL Bugs Early RISC-V formal verification : In an industry where missed corner cases can delay products by weeks or even months, LUBIS EDA recently demonstrated how formal verification can catch critical design bugs early — in some cases, within hours of the verification start. LUBIS EDA was able …