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Timeline Post Type Description

EXIST Transfer of Research funding secured

The project is awarded funding through Germany’s EXIST Transfer of Research programme — reserved for high-risk, high-potential research transfers with genuine commercial viability.

First validated on real processor and bus designs

A proof-of-concept is tested across a range of commercial processors and bus systems, demonstrating that the methodology works outside the lab. An early network of EDA and semiconductor industry contacts begins to form.

The idea takes shape

While completing their PhDs at the Chair of Electronic Design Automation at RPTU Kaiserslautern, Tobias and Michael identify a new hardware verification methodology with real industrial potential — and decide to build something around it.

Training Topics

  1. Abstraction vectors (time, functionality)
  2. AIP for protocols
  3. AIP orchestration
  4. BMC & IPG, invariants
  5. Codestyle
  6. Completeness
  7. Liveness property, safety property
  8. Non-determinism (abstraction technique)
  9. Response generation (abstraction technique)
  10. Scoreboard (abstraction technique)
  11. Signal cutting, blackboxing
  12. State space explosion and mitigation techniques
  13. SVA fundamentals
  14. Whitebox checking, blackbox checking, greybox checking
  15. Witness, vacuity, reachability

Become a leader in formal verification