Training

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Purpose

This program is designed to turn engineers into effective formal verification users—starting with the basics and building up to advanced design-level verification strategies. It blends theory, practical exercises, and team collaboration to make formal accessible, useful, and engaging. 

Training Contents

Introduction (1hr 30min)

What is formal verification? 
Why do we need formal verification? 
How is formal verification done?

Basic Training (16 hours) 

Designing of Assertion IP (AIP) and formulating formal properties 
Coverage Analysis 
Fundamental methods and concepts used in formal verification

Intermediate Training (16 hours) 

Formal Verification of irregular designs and basic design protocols.
Design complexity: It’s effect on formal verification and how it can be mitigated 
Abstraction techniques to mitigate design complexity

Advanced Training (16 hours) 

Analyze a project and create a verification plan 
Execute a small real life formal verification project

Format

How the training is structured

Short theory presentations to introduce each concept
The training is divided into assignments, each consisting of multiple tasks
Basic training focuses on the fundamentals of formal verification
Intermediate training covers commonly used design IPs and application of specific formal techniques
Advanced training focuses on applying formal verification in real-world scenarios

Learning Outcomes

What participants will learn

Confidently write and debug formal properties
Understand when and how to use formal verification effectively
Apply formal strategies to real-world IPs and protocols
Use advanced formal abstraction techniques to manage design complexity

Requirements

Prerequisites by training level

Basic training: No to minimal prior knowledge of formal verification required
Intermediate training: Some knowledge of SystemVerilog Assertions (simulation or formal engineers)
Advanced training: Strong knowledge of SystemVerilog Assertions (simulation or formal engineers)

Audience

Perfect for

Verification Engineers
Digital Designers
Simulation Engineers
Formal Verification Enthusiasts