(Senior) Formal Verification Engineer (m/f/d)

About the job

(Senior) Formal Verification Engineer (m/f/d)

At LUBIS EDA, we help our customers to find simulation-resistant bugs in their high-risk IP blocks. There is a large demand for formal methods, as it is a very efficient way to tackle the industry’s verification problems.

We developed a game-changing software solution that we use inhouse, making Formal Verification more intuitive and easier.

We are looking for people that want to become a Formal Verification (FV) expert.

Make a change and built a company together with us!

Skills:

• Basic knowledge in SystemVerilog/VHDL
• Beneficial: basic knowledge in SVA
• Business level English

For Senior level position:

• Advanced knowledge in SystemVerilog/VHDL
• Hands on verification experience with simulation or formal

Job Description:

a) Work in the start-up:

• Get trained in state-of-the-art formal verification techniques
• Be part of our verification and team and help us verifying customers designs
• Manage projects on your own
• Help with effort estimation and pricing
• Host a seminar/training with our customers and teach them about formal verification

b) Work on the start-up:

• Help our software team by providing feedback on our in-house software
• Take responsibility in R&D tasks, such as testing new products or trying new methodologies
• Visit conferences and engage in public discussions

What we offer:

• Attractive pay, stock options and budget for your own personal development
• Great work-life balance
• Chance to grow in leadership roles
• Remote or on-site work with monthly offline team meetings
• Young, intercultural team
• High-end work equipment
• Work with top-notch research facilities, customers and a unique software tool

Be an entrepreneur and not just an employee!