Formal verification engineer student

Your mission

  • 10h/week, from July 2025, hybrid
  • Be trained in state-of-the-art formal verification techniques
  • Be part of our verification team and help us verifying customers designs
  • Work on your own, with a team or lead your own project

Your profile

  • Ability to work independently and in a team
  • Basic knowledge in SystemVerilog/VHDL
  • Business level English
  • Beneficial: basic knowledge in SVA

Why us?

  • Flexible working hours that allow you to be the boss of your own work
  • Contribute your own ideas and manage your own development
  • Remote and on-site work
  • Regular team events in a young, dynamic, intercultural team
  • Hands-on insight into the working world and the growth of a startup

Apply for this position