How does LUBIS EDA Formal Verification help you?
As we are here to verify the high-risk blocks and give 100% coverage closure to your SoC designs. Our team of experts will work closely with you and help you in achieving your silicon design verification at a modest time by detecting hard-to-find bugs that shun simulation.
Key Issue
Do you know that 50% of the re-spinning is done due to the presence of functional bugs that jeopardize the important projects? Moreover, writing high-quality SVA properties is time consuming and requires expertise.
Our Approach
Focused on detecting simulation-resistant bugs through Formal Verification, we’ve developed a Formal Verification Methodology, that enables us to leverage our in-house software.
Objective
The core objective is to deliver an effective verification service to you to ensure you stay withing your project’s budget and timeline. We achieve full coverage, expose bugs and increase confidence in your design.
Our Approach
Focused on detecting simulation-resistant bugs through Formal Verification, we’ve developed a Formal Verification Methodology, that enables us to leverage our in-house software.
Key Issue
Do you know that 50% of the re-spinning is done due to the presence of functional bugs that jeopardize the important projects? Moreover, writing high-quality SVA properties is time consuming and requires expertise.
Objective
The core objective is to deliver an effective verification service to you to ensure you stay withing your project’s budget and timeline. We achieve full coverage, expose bugs and increase confidence in your design.
Formal Verification Plan
Our formal verification plan, which seeks to find defects in your high-risk blocks, is divided into three phases:
Setup Phase
This is the initial stage in which high-risk blocks are identified, verification targets are defined, the necessary effort is scoped, and most importantly, precise progress KPIs are established.
Execution Phase
The next step is the execution phase. During this time, the LUBIS EDA team carries out the verification plan and submits weekly feedback and on-the-spot bug reports.
Final Phase
In the final stage, our experts hand you the developed Verification IP (VIP) that accelerates run-time and integrated with existing regression tests to validate that a code change does not impact the existing functionality of the final product.
Industrial case studies
Let’s go through the real-life industrial case studies that would enable you to understand better how we execute Formal Verification Services at different design levels.
Custom DSP Control Unit
Provide a design bring-up environment
Verification Target
6k Lines of CodeDesign Size
3 Design Iterations16 Specification mismatches
Results
Design bring-up
Design and specification are still in process during the design bring-up. That’s why we provide a Verification IP to the designer based on the required specifications.
The provided VIP is used to verify that new changes don’t affect the existing functionality of the design. Additionally, it allows for identifying specification mismatches to update the VIP according to the changes.
Custom DSP Control Unit
Provide a design bring-up environment
Verification Target
6k Lines of CodeDesign Size
16 Specification mismatchesResults
Design bring-up
Design and specification are still in process during the design bring-up. That’s why we provide a Verification IP to the designer based on the required specifications.
The provided VIP is used to verify that new changes don’t affect the existing functionality of the design. Additionally, it allows for identifying specification mismatches to update the VIP according to the changes.
Design verification
When design and specifications are developed beforehand, we provide a VIP to validate the correct implementation of specified features.
SONET/SDH Framer
Feature Verification
Verification Target
27k Lines of CodeDesign Size
Complete Formal Coverage
Critical corner-case bugs,
Preventing a system
Results
Design verification
When design and specifications are developed beforehand, we provide a VIP to validate the correct implementation of specified features.
SONET/SDH Framer
Feature Verification
Verification Target
27k Lines of CodeDesign Size
Complete Formal CoverageResults
Commercial RISC-V core
Feature Testing: Decoding + Pipelining
Verification Target
4k Lines of CodeDesign Size
Specification compliance regarding RV32IM, RV32EFreedom of Data and Control Hazards
Results
Decoding
In this case, the assessment of specific and hard-to-verify features is made. Our team analyzes these features based on the scope of the project and the verification plan.
IP re-design
The demand for IP re-design is continuously increasing in industries. In fact, it has become the de-facto standard. Designers add new functionality to the IP resulting in a growing complexity of the designs. Therefore, it is considered necessary to re-factor the IP and implement performance improvements ultimately to preserve all existing functionality (documented or undocumented).
On-chip high-speed bus
Formal environment for a re-design
Verification Target
16k Lines of CodeDesign Size
Flipflops reduced by up to 50%
Functional equivalent re-implementation
Results
Commercial RISC-V core
Feature Testing: Decoding + Pipelining
Verification Target
4k Lines of CodeDesign Size
Freedom of Data and Control HazardsResults
Decoding
In this case, the assessment of specific and hard-to-verify features is made. Our team analyzes these features based on the scope of the project and the verification plan.
IP re-design
The demand for IP re-design is continuously increasing in industries. In fact, it has become the de-facto standard. Designers add new functionality to the IP resulting in a growing complexity of the designs. Therefore, it is considered necessary to re-factor the IP and implement performance improvements ultimately to preserve all existing functionality (documented or undocumented).
On-chip high-speed bus
Formal environment for a re-design