LUBIS EDA Software ensures

High-quality VIP



Formal Verification is done rightly to provide bug-free semiconductors with the help of software-based automation

What makes us different is the contemporary methodology of verifying a new IP-block. Our experts with the help of software-based automation generate high-quality verification IP in no time. This way we not only overcome the model’s shortcomings but also eradicate the possibilities of corner-case- bugs.

Our Expertise

Our team members have the expertise to run the software and analyze the outcomes properly to ensure the semiconductors are delivering high performance.                         

Writing High-quality VIP

With automation, we’ve made the process of generating high-quality SVA properties simpler. Moreover, the chance of the occurrence of functional bugs is also lessened.

Providing Scalability

LUBIS EDA’s tool flow provides the scalability of formal verification at large. The applicability of our FV techniques ensures the reliability of large-scale systems. Moreover, it is highly effective in finding functional bugs that are otherwise difficult to detect through traditional simulation and testing.


At LUBIS EDA, we use SystemC as an input to the tool with GUI that allows us to select the target formal tools to customize the generated properties. The standard SVA helps generate readily useful properties, which are loaded with DUT along with the selected formal tool to start the verification process.

This setup provides an efficient verification system that is time-saving and reliable. There is no need to convert the model into properties as the tool splits the complex properties into simple properties which minimize human errors and speed up the process.