Enabling an Agile Hardware Designflow

In the world of software development many companies switched to agile design methods, resulting in a faster time-to-market, less bugs and an increased ROI compared to traditional approaches.
This sounds great, so why is agile hardware development not a thing, yet?

There is vast variety of agile methods for software, e.g. Test-Driven Development (TDD), Extreme Programming (XP) or Continuous Integration (CI). 

The common denominator is the focus on quick iteration and fast feedback cycles. This makes rapid prototyping and unit testing elementary to ensure a continuous integration of features in an agile mannerTraditional hardware development does not leverage the full potential of these core elements.

Our mission is to provide tools that enable an agile hardware design flow.

LUBIS CONCILIUM

Abstraction beyond RTL

Many companies create virtual prototypes of their desired hardware systems. Usually, these models are used for architectural exploration or for early software development. However, these models are rarely used as golden models for design sign-off.

Why are people not using the faster, more abstract models for functional sign-off?
Simply, because verification results do not translate.
We are about to change this!

The first step to this change is LUBIS CONCILIUM.
By combining it with LUBIS PRIMIS or LUBIS VERITAS you’re able to ensure a sound relationship and thereby use your existing high-level model for sign-off.

Why should you use LUBIS CONCILIUM?

  • Allows sound modeling of your VP
  • Up to 100x faster than RTL simulation
  • Helps you refining your existing models to a sound model

What is LUBIS CONCILIUM?

  • SystemC framework
  • Designed for modeling untimed message passing
  • Tool support for assisted creation of your LUBIS CONCILIUM from an existing SystemC model
  • Extended synthesizable SystemC

 

LUBIS PRIMIS

Operation Level Synthesis … way more than HLS

The root of agile orignates in world of software development. Most agile methodologies share the idea of getting to a minimum valuable product (MVP) as fast as possible. This requires the creation of a placeholder, sometimes also called mocks or stubs, for elements that are not fully implemented, yet. This has two benefits within the development process.
The design team can:
• focus on new components and functionalities
• can get early feedback from other groups (e.g. customers, verification engineers?)
• step-by-step insert real implementations instead of the placeholders

Why are people not using rapid prototypes in the hardware domain?

The answer is simple: there is no tool that allows to generate functional correct hardware designs from an abstract model (e.g. ESL?).
Yes. There is HLS and it is strong when it comes to synthesizing algorithms. It has a weakness when it comes to synthesizing designs from a behavioral description.
And that’s where we offer a solution!

We invented, together with the TU Kaiserslautern, a new approach called Operation Level Synthesis (OLS) that allows us to synthesize correct-by-construction RTL designs from transaction-level models.

How does it work?

LUBIS PRIMIS takes your verified LUBIS CONCILIUM as an input and provides an easy-to-use interface to generate your desired hardware design in System Verilog, VHDL or SystemC-RTL.

After your automatic generation, your design team is free to replace generated prototypes with custom design or to alter the generated designs. Our LUBIS VERITAS tool provides you with a verification suite that allows you to quickly verify any changes to the prototype or to validate that your custom design adheres to the spec.

LUBIS VERITAS

Verify your designs quickly

Why are agile methods such a success in the world of software?
We believe that there is an easy answer: ultrafast feedback.

Especially, in Extreme Programming (XP) and Test-Driven Development (TDD) the development engineer receives feedback based on unit tests that are created before implementing the design. The purpose of the unit tests is to formalize the specification, documenting the code and to guide the design of the software. These methodologies lead to significantly less design bugs.

Why does a test-first approach not exist for hardware?

Most verification is done with simulation-based methodologies. However, simulation does not provide fast feedback and analyzing a failing test can be very time consuming. Aside from a functional verification, the unit tests in TDD are also supposed to document the implementation and aid the designer with the implementation. This is something that is almost impossible to archive with a simulation-based flow.

We propose a different methodology called Property-Driven Development (PDD). It’s based on formal Interval Property Checking (IPC). Each property describes an important operation of the design. By proving the property, it is checked, whether the design implements the according operation correctly.
However, writing properties is time consuming, complicated and error prone.
We offer a different solution to that. With LUBIS VERITAS the properties are directly generated from your LUBIS CONCILIUM.

How does it work?

LUBIS VERITAS generates a set of properties for each entity described in the specification. If all properties hold on the entity, the design is functional correct with respect to your specification. This establishes a formal relationship between the implementation and the high-level model. If the high-level model is verified, additional, functional verification of the RTL model is not necessary, because any functional bugs can be found within the high-level model.

What are the benefits?

  • Plan your design cycle: seamless tracking of progress makes estimating the remaining design time easier.
  • Documentation without overhead: The properties directly document your design because they are easy to read and to understand.
  • No more bug hunting: Functional bugs are an artefact of the past. The functional behavior is fully described by the LUBIS CONCILIUM.
  • Allows to shift the system verification task to a higher abstraction level and consequently less verification effort