The root of agile orignates in world of software development. Most agile methodologies share the idea of getting to a minimum valuable product (MVP) as fast as possible. This requires the creation of a placeholder, sometimes also called mocks or stubs, for elements that are not fully implemented, yet. This has two benefits within the development process.
The design team can:
• focus on new components and functionalities
• can get early feedback from other groups (e.g. customers, verification engineers?)
• step-by-step insert real implementations instead of the placeholders
Why are people not using rapid prototypes in the hardware domain?
The answer is simple: there is no tool that allows to generate functional correct hardware designs from an abstract model (e.g. ESL?).
Yes. There is HLS and it is strong when it comes to synthesizing algorithms. It has a weakness when it comes to synthesizing designs from a behavioral description.
And that’s where we offer a solution!
We invented, together with the TU Kaiserslautern, a new approach called Operation Level Synthesis (OLS) that allows us to synthesize correct-by-construction RTL designs from transaction-level models.
How does it work?
LUBIS PRIMIS takes your verified LUBIS CONCILIUM as an input and provides an easy-to-use interface to generate your desired hardware design in System Verilog, VHDL or SystemC-RTL.
After your automatic generation, your design team is free to replace generated prototypes with custom design or to alter the generated designs. Our LUBIS VERITAS tool provides you with a verification suite that allows you to quickly verify any changes to the prototype or to validate that your custom design adheres to the spec.