Formal Verification

Why Determinism still matters in the age of AI Verification

February 4, 2026

Why Determinism still matters in the age of AI verification The semiconductor industry faces increasing pressure to accelerate verification cycles while maintaining functional correctness. Recent advances in large language models have sparked interest in AI-generated assertions for formal verification. However, AI-generated assertions introduce quality risks that can undermine verification reliability: they may drift semantically between …

Assertion-first hardware design: where properties and intent come first

January 8, 2026January 7, 2026

Assertion-first hardware design: where properties and intent come first Compute is the bottleneck. Not ideas. Not talent. Compute. Every major leap we care about over the next decade, from AI to medicine to energy and mobility, depends on chips that deliver more performance with less power, on tighter schedules than ever. RTL can be produced …

What makes a verification environment ‘Formal-Ready’?

October 9, 2025October 7, 2025

What makes a verification environment “Formal-Ready”? Introduction: Why this matters now Chip complexity continues to rise across AI, automotive, and high-performance computing. Any bugs that escape pre-silicon verification into actual silicon can delay progress and harm reputation. Many teams still operate simulation-first environments that are excellent for constrained-random tests, but are not designed for porting …

Why are simulation-only verification flows failing modern chips?

January 19, 2026August 21, 2025

Why are simulation-only verification flows failing modern chips? Introduction Modern chip designs are pushing the boundaries of complexity, driven by demands in artificial intelligence, automotive, high-performance computing, and communications. The costs of advanced technology nodes such as 3nm FinFET mean that errors can cost hundreds of millions of dollars, or even more when delayed product …

Leveraging formal verification to find critical RTL bugs in a RISC-V core – a LUBIS EDA best practice

January 19, 2026July 23, 2025

News In an industry where missed corner cases can delay products by weeks or even months, LUBIS EDA recently demonstrated how formal verification can catch critical design bugs early — in some cases, within hours of the verification start. LUBIS EDA was able to find some undetected bugs that led to RTL changes in a …

Pitfalls in FPV

January 13, 2026December 18, 2024

Pitfall’s in FPV Formal verification allows engineers to employ mathematical methods to catch bugs in the RTL description of designs at an early stage in the development process. Formal verification tools find bugs by taking the RTL description and comparing it with an abstract, formal description of the design behavior, derived from the specification. SystemVerilog …

Safety vs Liveness properties in formal verification

January 13, 2026November 18, 2024

Safety vs Liveness properties in formal verification Formal verification is a crucial aspect of ensuring that digital systems behave as expected under all possible conditions. It relies on specifying and verifying properties to ensure the correctness of a design. These properties serve as formal statements that describe the expected behavior or constraints of a design …

Nondeterministic signals for complete and reliable design verification

January 19, 2026October 8, 2024

Nondeterministic signals for complete and reliable design verification Ensuring that the design under verification simulates all the possible scenarios is a challenging task. However, achieving this guarantees the completeness and correctness of the design. The state space of a design is the representation of all possible states that a design can go through during execution. …

Formal Verification abstraction methodologies

January 13, 2026September 12, 2024

Formal Verification abstraction methodologies Why end-to-end proofs? The adoption of formal verification has been on the rise, driven by the performance improvements of formal tools and the increasing demand for exhaustive verification, for example, required by safety standards. Employing end-to-end checks to formally verify a design block can facilitate the creation of formal verification IP …

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