Verification made in Germany

Verification made in Germany

Verification made in Germany

BENEFITS FOR YOU

Certainty Certainty

Save resources and avoid re-spins

Don‘t waste your teams‘ resources. Decrease your Time-To-Market

Coverage Coverage

Start simulating early. Reach your coverage goals in time

No more time spent with debugging due to functional errors

Coverage Coverage

automation Automation

Automatic generation of Verification IP

Correct-by-construction Verification IP

automation Automation

Use our solutions to:

Save resources and avoid re-spins

Start simulating early. Reach your coverage goals in time

Automatic generation of Verification IP

What you get:

Don‘t waste your teams‘ resources. Decrease your Time-To-Market

No more time spent with debugging due to functional errors

Correct-by-construction Verification IP

EASY ADDITION TO YOUR FLOW

LUBIS EDA works with your IP specification and your RTL design to generate a Verification IP (VIP) in the form of SVA-Properties. The VIP can later be used in simulation and/or formal verification.
We functionally verify your RTL with formal techniques and iteratively communicate bugs we find. You get short feedback cycles, reduce your time spent on RTL verification and higher-quality designs.

TARGET AREAS

DIGITAL IC DESIGN SOLUTIONS

IP Reuse

Do you already have your IC-design? But you want to create a newer, better version? With more features?


Generate a new verification IP for the updated design and find functional bugs early.


IP Refactoring

There exists a legacy IC-design that is often used?
It‘s neither lean nor efficient?
And nobody in your design team knows how it is structured?

Use the generated verification IP to clean up your code and retain full functional behaviour.

Top-Down Design

You need a new IP component? But you don‘t want to buy it? You want to develop it yourself?


Use the verification IP early from start to finish in your design process and incrementally develop your design.

Safety & Security

Your customers have new requirements? Your IC-design needs to be safe and secure?



The generated formal properties cover the entire functial behavior, document design intend and are easy to read.