This shortcomming cannot be repaired by using coverage metrics that tell which parts of the design were active during a simulation run, because even a simulation suite with a 100% coverage may, actually, cover only a fraction of the design’s full behaviour.
A possible solution for these issues is the integration of formal techniques into existing verification processes.
By design, formal techniques cover the complete design behaviour, but suffer from scalability issues. 💡
In a modernised verification flow,
1️⃣ Simulation would be used to find those bugs that are easy and quick to detect
2️⃣ Then formal methods are employed to find all corner case bugs in critical design components
What are your thoughts on that? We think, knowing about formal verification is essential for hardware engineers and developers who want to create reliable, secure, and compliant designs in an efficient way. 🙌