The recent Wilson Research Group Functional Verification Study analyzed how verification nowadays influences the way ASIC/IC projects are managed. The numbers indicate that companies spent a majority of time and resources on IC verification. Verification Engineers spend 41% of their time debugging bugs. Half of those bugs can be classified as functional or logic flaws. 68% of the project require at least one re-spin. This doesn`t have to be the case! We, as LUBIS EDA, will show you how to avoid costly re-spins in ASIC/IC projects by using formal verification early in the process.
Does your company have:
With our solution, we can ease that pain by:
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Let us democratise formal property generation
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